1. Field of Invention
The present invention relates to a fabrication method for a via plug. More particularly, the invention relates to a method of fabricating a self-aligned polysilicon via plug.
2. Description of Related Art
As the semiconductor technology progresses, the device keeps downsizing for entry into the deep micron process. While the integration of the device increases, it becomes less possible to provide sufficient area for fabricating required interconnects. In order to satisfy an increased need for interconnects after the size of the device is minimized, it is desirable to design multilevel interconnects with two or more layers in the very large scale integration (VLSI) technology. Also, it is necessary to form a hole, such as via hole in the insulating layer between two metal layers, and to fill the via hole with a conductive material so as to provide a connection between different metal layers.
As the demand for highly integrated device increases, it implies that the device need to be made more compact, with a smaller metal line and via plug or metal plug. Accordingly, a contact area between the via plug and the metal line becomes smaller. Moreover, in the conventional semiconductor process, the metal layer and the via opening are patterned using a photolithography and etching process. Therefore, once a misalignment occurs during the photolithography and etching process, the contact area between the via plug and the metal line is further reduced. It is known by those skilled in the art that a reduction in contact area between the via plug and the metal line creates a large local current density when the current flows through a junction between the metal line and the via plug. This leads to an electro-migration (EM) which reduces reliability of the device, and even results an open circuit in a worse scenario. The EM occurs as a result of electrons from the current that flowing through the metal line and bombarding a surface of the metal grains to break open connected metal grains. Thus, this leads to an open circuit. As the integration increases, together with a very large misalignment, the open circuit problem becomes more serious while the production yield is greatly reduced.
To better understand the problems caused by downsizing of the device, reference is made to FIGS. 1A through 1C, which illustrate a conventional process for fabricating a DRAM device.
Referring to FIG. 1A, a via opening 110 is formed on a dielectric layer 100.
Referring to FIG. 1B, a conductive layer 120, such as polysilicon layer or polycide layer is formed on the dielectric layer 100 so as to fill the via opening 110 with the conductive layer 120. The method for forming the conductive layer 120 includes chemical vapor deposition (CVD).
Referring to FIG. 1C, the conductive layer 120 is patterned to form a via plug 130, followed by forming a metal line 140 thereon.
The metal line 140 and the via opening 110 are patterned by a photolithography and etching process. Once a misalignment occurs, a contact area between the via plug 130 and the metal line 140 is reduced as shown in FIG. 1C. As the contact area between the via plug and the metal line is reduced, a large local current density is created when the current flows through a junction between the metal line and the via plug. This leads to an electro-migration (EM) which reduces reliability of the device, and even results an open circuit in a worse scenario.